CC driving method which has conventionally been employed in an active matrix liquid crystal display device is disclosed in, for example, Patent Literature 1. The following description first deals with CC driving with reference to the disclosure of Patent Literature 1 as an example.
FIG. 11 illustrates a configuration of a liquid crystal display device which carries out CC driving. FIG. 12 illustrates respective operating waveforms of various signals involved in the CC driving carried out by the liquid crystal display device of FIG. 11.
As illustrated in FIG. 11, the liquid crystal display device that carries out CC driving includes: an image display section 110; a source line driving circuit 111; a gate line driving circuit 112; and a CS bus line driving circuit 113.
The image display section 110 includes: a plurality of source lines (signal lines) 101; a plurality of gate lines (scan lines) 102; switching elements 103; pixel electrodes 104; a plurality of CS (capacity storage) bus lines (common electrode lines) 105; storage capacitors 106; liquid crystal sections 107; and a counter electrode 109. The switching elements 103 are provided near respective intersections of the source lines 101 with the gate lines 102. The switching elements 103 are each connected to one of the pixel electrodes 104.
The CS bus lines 105 each extend in parallel to the gate lines 102 so as to form a pair with one of the gate lines 102. The storage capacitors 106 each have (i) a first terminal connected to a corresponding one of the pixel electrodes 104 and (ii) a second terminal connected to a corresponding one of the CS bus lines 105. The counter electrode 109 is provided so as to face the pixel electrodes 104 via the respective liquid crystal sections 107.
The source line driving circuit 111 is provided so as to drive the source lines 101. The gate line driving circuit 112 is provided so as to drive the gate lines 102. The CS bus line driving circuit 113 is provided so as to drive the CS bus lines 105.
The switching elements 103 each include amorphous silicon (a-Si), polycrystalline polysilicon (p-Si), or single crystal silicon (c-Si), for example. As a result of this arrangement, a capacitor 108 is created between a gate terminal and a drain terminal of each of the switching elements 103. Because of the capacitor 108, a phenomenon occurs in which a potential of each pixel electrode 104 is shifted to a negative side by a gate pulse supplied from a corresponding one of the gate lines 102.
As illustrated in FIG. 12, a gate line 102 of the above liquid crystal display device has a potential Vg which is (i) set at Von only during its horizontal scanning period (H period), that is, only while the gate line 102 is being selected, and (ii) maintained at Voff during the other period. A corresponding source line 101 has a potential Vs having a waveform which (i) has an amplitude that differs depending on a video signal for each display and (ii) has a polarity that is reversed every H period across a central potential of a counter electrode potential Vcom and that is reversed between consecutive H periods for any given gate line 102 (line inversion driving). Note that since FIG. 12 assumes a case in which a uniform video signal is inputted, the potential Vs oscillates at a constant amplitude.
A corresponding pixel electrode 104 has a potential Vd while the potential Vg is set at Von which potential is identical to the potential Vs of the source line 101 because a corresponding switching element 103 is conductive during such a period. The potential Vd is then slightly shifted to the negative side through the gate-drain capacitor 108 at a fall of the potential Vg to Voff.
A CS bus line 105 corresponding to the gate line 102 has a potential Vc which is set at a Ve+ level during (i) a first H period, that is, while the gate line 102 is being selected, and (ii) a second H period, which is subsequent to the first H period. The potential Vc is switched to a Ve− level at the beginning of a third H period, which is subsequent to the second H period. The potential Vc is maintained at the Ve− level until the beginning of a next field. Because of the above switching, the potential Vd is shifted to the negative side through a corresponding storage capacitor 106.
With the above arrangement, the potential Vd oscillates at an amplitude larger than an amplitude of the potential Vs, and the potential Vs thus oscillates at a smaller amplitude. As such, the source line driving circuit 111 can have a simplified circuit configuration and a reduced power consumption.